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Job Description Experience with Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction. Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and power recovery. Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates Synthesis Tools: Synopsys DC/DCG/FC. Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/PrimeClosure, Cadence Tempus. Scripting: TCL, Perl, or Python. This role expects you to be responsible for closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while managing ECO tasks. Your role may include extraction and STA flow development, convergence strategies We are a company committed to creating inclusive environments where people can bring their full, authentic selves to work every day. We are an equal opportunity employer that believes everyone matters. Qualified candidates will receive consideration for employment opportunities without regard to race, religion, sex, age, marital status, national origin, sexual orientation, citizenship status, disability, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or recruiting process, please send a request to [email protected] . The EEOC "Know Your Rights" Poster is available here ( . To learn more about how we collect, keep, and process your private information, please review Insight Global's Workforce Privacy Policy: . Skills and Requirements Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and power recovery. Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates Synthesis Tools: Synopsys DC/DCG/FC. Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/PrimeClosure, Cadence Tempus. Scripting: TCL, Perl, or Python. Background in ASIC Frontend and RTL Design null We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal employment opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment without regard to race, color, ethnicity, religion,sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military oruniformed service member status, or any other status or characteristic protected by applicable laws, regulations, andordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request to [email protected].

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